LPU - Lovely Professional University
What you'll learn

This course is specially designed for the students who want to make their digital circuit design fundamentals strong which is desirable in every circuit design industry. Learning Verilog HDL for circuit design and simulation with AMD tool make the student industry ready. The course starts with simple logic gates towards application specific project in very appropriate staircase manner to make learning easy and effective. Circuit design skill development techniques are inbuilt in this course making student free from any sort of cramming or rote learning of the designed circuits.

  • Digital Vs Analog Signals Boolean Algebra, Logic Gates, Function Implementation using logic gates, SOP-POS, K-MAPs
  • Introduction to Verilog HDL, Levels of Abstraction ,Adders -Half & Full ,Subtractors- Half & Full, Design of Multiplexer-Demultiplexer
  • Adder/Subtractor Verilog coding using Gate level modelling, Multiplexer and Demultiplxer Verilog coding using Gate level modelling, Function Implementation using Multiplexer and Demultiplxer, Test Bench writing and simulation with AMD Tool
  • Data Operators, Adder/Subtractor Verilog coding using Dataflow modelling, Multiplexer and Demultiplxer Verilog coding using Dataflow modelling, Design of Decoder & Function Implementation using Decoder, Verilog coding using Gate level & Dataflow modelling
  • SR,JK,T,D Flip-Flops, Edge triggering & Master Slave Flip-Flops, Verilog Implementation of Flip-Flops, Asynchronous Counters Design,Verilog Implementation of Asynchronous Counters
  • Synchronous Counters Design, Verilog Implementation of Synchronous Counters, CA-2, Shift Registers, LFSR & Ring and Jhonson Counter
  • Mealy FSM state diagram, Sequence Detector using Mealy and Circuit designing, Verilog Implementation of Sequence Detector using Mealy, Moore FSM state diagram, Sequence Detector using Moore and Verilog implementation
  • NMOS-PMOS as switch & CMOS as Inverter, Function implementation using CMOS, Verilog Implementation of logic gates using switch level modelling, Transmission Gate using CMOS, 2X1 MUX implementation, CA-3
  • Verilog Code for Car Parking System, Verilog Code for Traffic Light Controller, Vending Machine Design using Verilog, Digital Clock using Verilog, Booth Multiplier using Verilog

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Dr. Sobhit Saxena
Professor

Dr. Sobhit Saxena has completed his Ph.D. from IIT Roorkee in 2018. He did his M.Tech. in VLSI and B.E. in Electronics and Communication Engineering. He has a vast teaching experience of more than 15 years in various colleges and universities. Currently, he is working as Professor in School of Electronics and Electrical engineering, Lovely Professional University. He has been awarded the “Perfect Award” four times in consecutive years for achieving 100% result. He has published more than 40 research papers in SCI/Scopus indexed journals and reputed international conferences/Non-indexed journals. He has filled 9 patents, published several edited/authored books and book chapters. His area of expertise includes Analog & Digital VLSI Design, modeling and simulation of CNT based interconnects.